Cambridge, Massachusetts
Feb. 2, 2002
Immediately precedes the
Eighth International Symposium on High Performance Computer Architecture
Sponsored
by the IEEE
Computer Society
Russell Clapp, IBM
rclapp@us.ibm.com
Kimberly Keeton, Hewlett-Packard Laboratories
kkeeton@hpl.hp.com
Ashwini Nanda, IBM TJ Watson Research Center
ashwini@watson.ibm.com
Building on the positive feedback enjoyed by the previous Workshops on Computer Architecture Evaluation using Commercial Workloads, this fifth workshop will again bring together researchers and practitioners in computer architecture and commercial workloads from industry and academia. In the course of one day, we will discuss work-in-progress that utilizes commercial workloads for the evaluation of computer architectures. By discussing this ongoing research, the workshop will expose participants to the characteristics of commercial workload behavior and provide an understanding of how commercial workloads exercise computer systems.
The tentative final program for the workshop is listed below. There will be plenty of time for audience participation. A proceedings document containing either full papers or extended abstracts for each presentation will be provided for registered attendees at the workshop. Electronic versions will be available via this web site sometime after January 21, 2002.
Tentative Final Program
8:00 am - 8:15 am
Registration
8:20 am - 8:30 am
Introductory
Comments
8:30 am – 10:00 am
Evaluation of Shared Cache Architectures for TPC-H
Michel Dubois, Jaeheon Jeong, Shahin Razeghia, Mahsa Rouhaniz and Ashwini Nanda
University of Southern California
Precise and Accurate Processor Simulation
Harold W. Cain, Kevin M. Lepak, Brandon A. Schwartz and Mikko H. Lipasti
University of Wisconsin - Madison
New Challenges in Benchmarking Future Processors
Shubhendu S. Mukherjee
Intel Corporation
10:00 am - 10:30 am
Coffee
Break
10:30 am – 12:00 pm
Session
2: Methodologies
Alaa R. Alameldeen, Carl J. Mauer, Min Xu, Pacia J. Harper, Milo M.K. Martin, Daniel J. Sorin, Mark D. Hill and David A. Wood
University of Wisconsin - Madison
How Input Data Sets Change Program Behaviour
Lieven Eeckhout, Hans Vandierendonck, Koen De Bosschere
Department of Electronics and Information Systems (ELIS)
Ghent University – Belgium
Benchmarking Web Server Architectures: A Simulation Study on Micro
Performance
Haiyong Xie, Laxmi Bhuyan and Yeim-Kuan Chang
Department of Computer Science & Engineering
University of California - Riverside
12:00 am - 1:30 pm
Lunch
1:30 pm – 3:00 pm
Session
3: Architecture Evaluation and Modeling
Compressibility Characteristics of Address/Data Transfers in Commercial
Workloads
Krishna Kant and Ravi Iyer
Enterprise Architecture Laboratory
Intel Corporation
Performance Workloads in a Hardware Multi Threading Environment
Bret Olszewski and Octavian F. Herescu
IBM
A Processor Queuing Simulation Model for Multiprocessor System
Performance Analysis
Thin-Fong Tsuei and Wayne Yamamoto
Sun Microsystems
3:00 pm - 3:30 pm
Coffee
Break
3:30 pm - 5:00 pm
Session
4: Workload Characterization
Performance Analysis of Speech Recognition Software
Chunrong Lai, Shih-Lien Lu and Qingwei Zhao
Intel Corporation
Comparison of Memory System Behavior in Java and Non-Java Commercial
Workloads
Morris Marden, Shih-Lien Lu, Konrad Lai Mikko Lipasti
University of Wisconsin – Madison and Intel Corporation
Characterizing TPC-H on a Clustered Database Engine from the OS
Perspective
Yanyong Zhang, Jianyong Zhang, Anand Sivasubramaniam, Chun Liu and
Hubertus Franke
The Pennsylvania State University and IBM T.J. Watson Research Center
5:00 pm
Participant
Feedback
Closing
Remarks