Seventh Workshop on Computer Architecture Evaluation using Commercial Workloads (CAECW-7)


Madrid, Spain

Sunday, February 15, 2004

 

Immediately precedes the

 Tenth International Symposium on High Performance Computer Architecture (HPCA-10)

IEEE Computer SocietySponsored by the IEEE Computer Society, TCCA

Workshop webpage:  http://tesla.hpl.hp.com/caecw04/

 

The function of this workshop is the discussion of work-in-progress that utilizes commercial workloads for the evaluation of computer architectures.  By discussing this ongoing research, the workshop will expose participants to the characteristics of commercial workload behavior, provide an understanding of how commercial workloads exercise computer systems and potentially help establish methodologies for measuring, modeling and analyzing the execution time characteristics of these workloads.

The tentative final program for the workshop is listed below. The program includes refereed paper presentations, invited talks (including a keynote), and plenty of time for audience participation. Hard copies of the proceedings will be provided for registered attendees at the workshop; an electronic version of the full proceedings is available as a pdf file here (~7 MB).

 Tentative Final Program

 

8:00 - 8:30

Registration

8:30 - 9:30

Session 1: Keynote

 

Workload Characterization:  Can It Save Computer Architecture and Performance Evaluation?

Lizy K. John (University of Texas at Austin)

9:30 - 10:30

Session 2:  Network Processing

 

TCP/IP Cache Characterization in Commercial Server Workloads

Li Zhao, Ramesh Illikkal, Srihari Makineni (Intel) and Laxmi Bhuyan (University of California)

 

Increased Packet Processing Efficiency for Network Intensive Server Workloads (Invited paper)

Greg J. Regniers (Intel Labs)

10:30 - 11:00

Coffee Break

11:00 - 12:30

Session 3: Workload Characterization

Characterization of L3 Cache Behavior of Java Application Server

Nirut Chalainanont, Eriko Nurvitadhi (Oregon State University),

Kingsum Chow and Shih-Lien Lu (Intel)

 

Case Studies: Memory Behavior of Multithreaded Multimedia Applications

Lu Peng (University of Florida), Justin Song, Steven Ge, Yen-Kuang Chen, Victor Lee (Intel),

Jih-Kwon Peir (University of Florida) and Bob Liang (Intel)

 

Workload Studies in Support of an EPIC-based Fault-Tolerant System Design (Invited paper)

Pankaj Mehra, Rahul Nim (Hewlett-Packard) and Benjamin J. Brothers (University of Illinois)

12:30 - 14:00

Lunch

14:00 - 15:30

Session 4: Microprocessor Analysis and Design

Power-Performance Efficiency Design of a High-Performance Microprocessor for Decision Support Workloads

Pedro Trancoso (University of Cyprus)

 

Many Benchmarks Stress the Same Bottlenecks

Hans Vandierendonck and Koen De Bosschere (Ghent University)

 

Entropy-based Characterization of Program Phase Behaviors

Mingqiu Sun, Joe E. Daly, Hong Wang and John P. Shen (Intel)

15:30 – 16:00

Coffee Break

16:00 - 17:30

Session 5: Multiprocessor Workloads

Characterization of an IMAP Server on a Shared-Memory Multiprocessor

Pranay Koka and Mikko Lipasti (University of Wisconsin—Madison)

 

Comparing OLTP Scaling Behavior on Intel Xeon and Itanium 2 Processors

Richard Hankins (Intel and University of Michigan), Murali Annavaram (Intel), Brian Hirano (Oracle),

Jignesh Patel (University of Michigan) and John Shen (Intel)

 

Evaluating a $2M Commercial Server on a $2K PC and Related Challenges (Invited paper)

Mark Hill (University of Wisconsin—Madison)

17:30

Participant Feedback

Closing Remarks

Workshop organizers

Past workshops